D5: Smart Meter Design Exercise

This was the second of the two group projects in Year 2 of the degree. Once again it was done in a group of 6. The members of the group were Anurag Sahare, Sam Evans, Yue Shuen, Tianyang Li, Iris Gao, and myself. This project involved producing a complete product of a micro-grid smart meter to prioritize power usage. The scenario was a hospital environment that had different operations on different loads. We had to design the entire product from the ground up, this meant housing, the power supply, the interface circuitry, the control algorithm and the graphical user interface. The product had to interface to a TTL logical board that had a simulated scenario for a 24 hour period (ran at a rate of 1 minute to an hour in the simulation) and we had to minimize the amount of losses in life (as if each load lost power when it required it, there was an associated loss).

The final smart meter box

Once again, since there were distinct tasks we decided to split the team up and assign responsibilities. This project was different to the last as we had a budget and had a stricter time management. As a result we were recommended to give roles of Project Manager, Budget Manager and Secretary. As a result, I put myself forward for PM and got it. This was something that I wanted to do as working in corporate environment for my summer jobs I was hoping this experience would give me an upper hand on managing the project. It was also a good experience for me in learning how to manage people and setting expectations of the team.

We then decided that we should once again split the jobs up evenly and all come together to work on the final piece. This meant the housing, power supply and coding were all undertaken by pairs of lab partnerships. We had 3 milestones in the project where a certain aspect of the project was evaluated and so each team had a different timeline to work to, but also needed to work harmoniously to bring it all together for the final review where the product was evaluated as a whole.

The development of the Graphical User Interface

To cut an extremely long and stressful story short (and to save on many of the technical details along the way), we hit every deadline producing a more than satisfactory result each time. We managed to produce an algorithm that in the end saved 240/250 people in a day, and would have reduced catastrophe if there was an all out power outage. We had a housing that was protective enough from water than when it was tested, the electronics stayed on and nothing had to be remade due to water damage, and we had a power supply that ran at just above the power draw specification but produced a bright screen and our interface, after some stressful debugging on the final day worked flawlessly to interface between our control board and the TTL logic.

Overall Result: 73%

D2: Integrated Circuit Design

This was the first of our two group projects in Year 2 of the degree, each of which were done in teams of 6. My team consisted of Anurag Sahare, Byron Theobald, Hawk Roy Wood, Ben West, Oliver Dalziel, and myself. This particular project involved designing an integrated circuit (IC) to be created on a silicon chip and then testing it once it had been fabricated. The specifications meant we were required to have an inverter, a 4-bit adder, sequence decoder, ring oscillator and an X-bit multiplier. (We were able to choose between 4 to 8 bits depending on the space we had and how long it would take us to fit it in).

We were required to use L-edit and S-edit for the layout and schematic respectively. We split each requirement into a team (a lab partnership), one to do the layout, the other to do the schematic. The reason we did this was because the inverter was already designed, so we had 3 circuits to design before all coming together to work on the multiplier. In the end we used a hierarchical design so that we could move it about in the overall schematic to give us the most flexibility for our multiplier. Due to this fact we were able to produce a 7-bit multiplier schematic. The chip was laid out as follows:

The blackbox schematic for the IC

In the second semester, we had to test our design. To do this, we designed test vectors to be ran on the input and output pins. The vectors contained timings for the changing of the input pins and the expected results on the output pins. Any deviation from the vectors were reported. I am glad to report that after 5 months of anticipation and hoping we had designed our chip correctly, all our test vectors returned a 0 error report. This meant that as we had defined, the chip was working as intended.

We were also able to ensure the vectors would pick up errors by testing other sites on the chip that did not have same functionality as ours. When testing on these sites we received the correct error reporting from the vectors. We also had to produce a manual test which including a binary input console that did the multiplication and tested the output. This meant the invigilator could input whatever test values they wanted and the system would automatically test the result. Our methodology, process and testing was then put in a report. We then received grading for each section of the project, which was as followed:

• • Schematic Design: 10.3/10
  • L-edit Design: 10.3/10
  • Chip Functionality: 20.6/10
  • Design Stage: 40+/40 (it was possible to get more than the maximumdepending on how much further than the standard 4-bit multiplier designed)
• • Golden Design: 10/10
  • Test Vectors: 5.5/10
  • System Demonstration: 10/10
  • Testing Stage: 25.5/30
• • Technical Approach: 75±5 / 100
  • Testing and Evaluation: 75±5 / 100
  • Report writing, structure, format: 80±5 / 100
  • Report: 72%
• Overall Results: 89.5%